// Copyright (C) 1953-2022 NUDT
// Verilog module name - control_stream_switching.v 
// Version: V4.1.0.20221212
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//          
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module control_stream_switching
(
        i_clk             ,   
        i_rst_n           ,
        
        i_local_or_remote_ctrl,

        iv_data_lmp        ,
        i_data_wr_lmp      ,    
        ov_data_lmp        ,        
        o_data_wr_lmp      , 

        iv_data_tsc        ,
        i_data_wr_tsc      ,    
        ov_data_tsc        ,        
        o_data_wr_tsc      ,

        iv_data_tse        ,
        i_data_wr_tse      ,    
        ov_data_tse        ,        
        o_data_wr_tse      ,          

        iv_data_ton       ,
        i_data_wr_ton     ,
        
        iv_data_rep       ,
        i_data_wr_rep             
);

// I/O
// clk & rst
input                   i_clk             ;
input                   i_rst_n           ;

input                   i_local_or_remote_ctrl;

input   [8:0]           iv_data_lmp        ;
input                   i_data_wr_lmp      ; 
output  [8:0]           ov_data_lmp        ; 
output                  o_data_wr_lmp      ; 

input   [8:0]           iv_data_tsc       ;
input                   i_data_wr_tsc     ;
output  [8:0]           ov_data_tsc       ;
output                  o_data_wr_tsc     ;

input   [8:0]           iv_data_tse       ;
input                   i_data_wr_tse     ;
output  [8:0]           ov_data_tse       ;
output                  o_data_wr_tse     ;

input   [8:0]           iv_data_ton       ;
input                   i_data_wr_ton     ;

input   [8:0]           iv_data_rep       ;
input                   i_data_wr_rep     ; 

wire    [8:0]           wv_data_ton_pdi2cps3    ;
wire                    w_data_wr_ton_pdi2cps3  ;

wire    [8:0]           wv_data_rep_pdi2cps1    ;
wire                    w_data_wr_rep_pdi2cps1  ;
packet_dispatch_1to2 ton_dispatch_1to2_inst
(
    .i_clk        (i_clk                 ),
    .i_rst_n      (i_rst_n               ),
	                          
	.i_ctrl       (i_local_or_remote_ctrl),//1'b0:local;  1'b1:remote
                             
    .iv_data      (iv_data_ton       ),
	.i_data_wr    (i_data_wr_ton     ),
                          
	.ov_data_0    (  ),//1'b0:local 
	.o_data_wr_0  (  ),
                      
	.ov_data_1    (wv_data_ton_pdi2cps3  ),//1'b1:remote
	.o_data_wr_1  (w_data_wr_ton_pdi2cps3)    
);

packet_dispatch_1to2 report_dispatch_1to2_inst
(
    .i_clk        (i_clk                 ),
    .i_rst_n      (i_rst_n               ),
	                          
	.i_ctrl       (i_local_or_remote_ctrl),//1'b0:local;  1'b1:remote
                             
    .iv_data      (iv_data_rep       ),
	.i_data_wr    (i_data_wr_rep     ),
                          
	.ov_data_0    (  ),//1'b0:local 
	.o_data_wr_0  (  ),
                      
	.ov_data_1    (wv_data_rep_pdi2cps1  ),//1'b1:remote
	.o_data_wr_1  (w_data_wr_rep_pdi2cps1)    
);

control_packet_switch tse_interface_switch//cds1
(
        .i_clk           (i_clk      ),   
        .i_rst_n         (i_rst_n    ),
                                     
        .iv_data_0       (iv_data_lmp   ), 
        .i_data_wr_0     (i_data_wr_lmp ), 
        .ov_data_0       (ov_data_lmp   ),       
        .o_data_wr_0     (o_data_wr_lmp ), 
                                     
        .iv_data_1       (iv_data_tsc  ),
        .i_data_wr_1     (i_data_wr_tsc),
        .ov_data_1       (ov_data_tsc  ),        
        .o_data_wr_1     (o_data_wr_tsc),  
                                     
        .iv_data_2       (wv_data_rep_pdi2cps1  ),
        .i_data_wr_2     (w_data_wr_rep_pdi2cps1),

        .iv_data_3       (wv_data_ton_pdi2cps3  ), 
        .i_data_wr_3     (w_data_wr_ton_pdi2cps3), 

        .iv_data_4       (iv_data_tse  ), 
        .i_data_wr_4     (i_data_wr_tse), 
        .ov_data_4       (ov_data_tse  ),         
        .o_data_wr_4     (o_data_wr_tse)          
);
endmodule